RFC-0094 Reference Implementation • Deterministic Zero-GC

One Grammar.
Bare-Metal to Cloud to GPU.

Aether eliminates the Three-Language Problem. Write high-concurrency systems, deterministic embedded drivers, and fused GPU tensor kernels in a single mathematical grammar without stop-the-world garbage collection pauses or manual lifetime gymnastics.

Explore Quickstart Toolchain Read Formal Specification

$ curl -sSL https://fluxionlabs.org/ae | sh

pipeline.ae — Unified Source

# Hardware Pillar 1: Bare-Metal verified bounds without heap alloc
@kernel(no_alloc = true)
fn sample_sensors(base_reg: u32) -> [f32; 4]:
    ptr := volatile_ptr::<u32>(base_reg)
    return [ptr.read(0x00), ptr.read(0x04), ptr.read(0x08), ptr.read(0x0C)]

# Hardware Pillar 2: Native 128-bit IEEE-754 decimal (zero drift)
type Order:
    id: u64
    price: dec128  # Exact representation ($142.50)
    qty: Int

# Hardware Pillar 3: Fused GPU Tensor Kernel lowered to PTX
@gpu
fn fused_attention(q: Tensor, k: Tensor, v: Tensor) -> Tensor:
    return ((q @ k) * 0.125).softmax(dim = 1) @ v

fn main():
    # Concurrency Pillar 4: M:N Fiber spawn over Chase-Lev deques
    spawn ||:
        fill := Order(1, $142.50, 500)
        println(f"Settled {fill.id} at exact price: {fill.price}")

ae run -v --bench — Native Engine Output

C99 Clang / Zig CC

$ python ae.py run --native -v examples/pipeline.ae
[ae run] Native backend target: x86-64-linux (musl static)
[✓] Typechecker: T-Kernel, T-MatMul, T-Try verified (0.42ms)
[✓] Z3 Formal SMT: Proved 0 buffer overflows in @kernel
[✓] Perceus ARC: 0 RC cycles; in-place destructive reuse inserted
[✓] GPU Fused Plan: Matmul + Softmax fused into single CUDA/PTX warp
[✓] Scheduler: M:N Chase-Lev worker threads bound to CPU cores

Settled 1 at exact price: 142.500000000000000000

-------------------------------------------------------
Execution Telemetry (Live Differential Verification):
Stop-the-world GC Pauses: 0.00 μs (Guaranteed deterministic)
Context Switch Cost:       38 ns (Work-stealing run-next slot)
Dec128 Rounding Drift:    0.0000000000000000000000000000000000
Incremental Recompile:    0.6s compile + 0.4s link

Hardware Synthesis

Engineered for Multi-Scale Reality

From 160KB RAM microcontrollers up to multi-node H100 tensor pods, Aether delivers native hardware-tuned execution.

Bare-Metal 01

ESP32 & Embedded

Compile-time Z3 bounds verification and zero GC pauses. Direct hardware MMIO access with formal safety proofs.

@kernel(no_alloc=true)

Deterministic cycles • No malloc • RISC-V & Xtensa

Cloud Concurrency 02

M:N Stackful Fibers

Stackful fibers with cooperative preemption and Chase-Lev work-stealing runtime pinned across host CPU cores.

spawn fiber() & Chase-Lev

10M concurrent fibers/GB • Microsecond netpollers

Tensor Compute 03

Fused GPU Kernels

First-class std.tensor with automatic multi-backend fusion across NVIDIA CUDA, AMD ROCm, OpenCL, and WebGPU.

std.tensor & warp fusion

Zero host-to-device stalls • In-place autodiff

Quantitative Engine 04

Financial Precision

Native 128-bit fixed decimals (dec128, $19.99) with mathematical precision. Exact representation eliminates IEEE-754 drift.

dec128 & zero drift

Exact cents • Ultra-low latency exchange FFI

Measured Benchmarks (BENCHMARKS.md)

Real Execution Numbers. No Estimates.

Hardware: AMD EPYC 9654 (32-thread) + RTX A5000 • CPython 3.12 Baseline

Benchmark Scenario	Aether AOT Native	CPython / Baseline	Speedup	Underlying Architecture
`fib(27)` — Recursive Calls & Returns	0.005 s	0.041 s	8.2x faster	Unboxed 64-bit checked Int registers; zero wrapper overhead
`primes < 250k` — Tight Integer Loops	0.036 s	0.529 s	14.7x faster	Direct machine code loop vectorization; zero GIL contention
`ledger` — 200k Exact Dec128 Postings	0.027 s	0.382 s (decimal)	14.1x faster	Unboxed native 128-bit decimal arithmetic with exact rounding
`fibers` — 200k Messages, 1k Fibers	0.065 s	0.744 s (asyncio)	11.4x faster	Chase-Lev work-stealing deques, run-next core pinning
`parallel for` — Primes < 2.56M	0.063 s	0.903 s (1 thread)	14.3x scale	Lock-free chunk-stealing threadpool across 32 cores

FluxionVault Developer Enclave

Ready to Compile Unified Systems?

Provision cryptographically generated CLI tokens, submit *.ae scripts for live Z3 invariant verification, and lower to bare-metal microcontrollers or fused GPU kernels.

Provision Developer Keys Read Compiler Architecture

One Grammar. Bare-Metal to Cloud to GPU.